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ESH10000025 - GPIO Module

Overview

The ESH10000025 is a general-purpose I/O module providing 96 bidirectional digital channels organized into 6 banks with configurable voltage levels per bank.

Description

The GPIO Module provides 96 digital I/O channels across 6 independent banks (16 channels each), with per-bank voltage level control. This module is ideal for flexible digital interfacing, custom signal routing, and DUT control applications.

Key Features:

  • 96 Digital I/O Channels: Organized into 6 banks of 16 channels

    • Bidirectional capability (IN/OUT configurable per channel)
    • Configurable pull-up/pull-down resistors
    • Push-pull or open-drain output modes
    • Bank-level register access for parallel operations
  • 6 Voltage Output Controls (VIO_BANK): Independent voltage supply per bank

    • Range: 1.2V to 5.0V
    • 12-bit DAC resolution
    • Allows interfacing with different logic families simultaneously
  • Bank Register Interface: Direct 8-bit register read/write per bank (A/B ports)

    • Enables fast parallel I/O operations
    • Hex or decimal value support
    • Automatic GPIO update on register write

Hardware Details

GPIO Expanders:

  • Chip: NXP PI4IOE5V6416 (6 chips)
  • Channels per chip: 16 (2 ports × 8 pins)
  • Total channels: 96
  • I²C Addresses:
    • U6: 0x20 (I2C0) - GPIO00-15
    • U7: 0x21 (I2C0) - GPIO16-31
    • U8: 0x20 (I2C1) - GPIO32-47
    • U9: 0x21 (I2C1) - GPIO48-63
    • U10: 0x20 (I2C2) - GPIO64-79
    • U11: 0x21 (I2C2) - GPIO80-95
  • Communication: I²C bus

Voltage DAC:

  • Chip: Microchip MCP47FEB18 (MCP47FXBX family)
  • Channels: 6 outputs (2 DACs × 3 channels, interleaved addressing)
  • Resolution: 12-bit
  • I²C Address: 0x60
  • Voltage Range: 1.2V - 5.0V (double DAC range mode enabled)
  • Default Value: 1.8V per bank

I²C Multiplexer:

  • Chip: TI PCA9540 or similar
  • Address: 0x70
  • Purpose: Routes I²C bus to internal I2C0, I2C1, I2C2 segments

Channel Naming Convention

All channels follow the naming pattern: {ModuleIndex}.ESH10000025.{ChannelName}

Example: Module at position 0, GPIO channel 42 would be: 0.ESH10000025.GPIO42

User-Accessible Channels

Channel Name Type Direction Usage Description
GPIO00-GPIO15 Digital IN/OUT UserAllocatable Bank 0 GPIO channels (U6)
GPIO16-GPIO31 Digital IN/OUT UserAllocatable Bank 1 GPIO channels (U7)
GPIO32-GPIO47 Digital IN/OUT UserAllocatable Bank 2 GPIO channels (U8)
GPIO48-GPIO63 Digital IN/OUT UserAllocatable Bank 3 GPIO channels (U9)
GPIO64-GPIO79 Digital IN/OUT UserAllocatable Bank 4 GPIO channels (U10)
GPIO80-GPIO95 Digital IN/OUT UserAllocatable Bank 5 GPIO channels (U11)
VIO_BANK0 Analog OUT UserAllocatable Voltage supply for GPIO00-15 (1.2V-5.0V)
VIO_BANK1 Analog OUT UserAllocatable Voltage supply for GPIO16-31 (1.2V-5.0V)
VIO_BANK2 Analog OUT UserAllocatable Voltage supply for GPIO32-47 (1.2V-5.0V)
VIO_BANK3 Analog OUT UserAllocatable Voltage supply for GPIO48-63 (1.2V-5.0V)
VIO_BANK4 Analog OUT UserAllocatable Voltage supply for GPIO64-79 (1.2V-5.0V)
VIO_BANK5 Analog OUT UserAllocatable Voltage supply for GPIO80-95 (1.2V-5.0V)
REGBANK_0A Register OUT UserAllocatable Direct 8-bit register access to GPIO00-07
REGBANK_0B Register OUT UserAllocatable Direct 8-bit register access to GPIO08-15
REGBANK_1A Register OUT UserAllocatable Direct 8-bit register access to GPIO16-23
REGBANK_1B Register OUT UserAllocatable Direct 8-bit register access to GPIO24-31
REGBANK_2A Register OUT UserAllocatable Direct 8-bit register access to GPIO32-39
REGBANK_2B Register OUT UserAllocatable Direct 8-bit register access to GPIO40-47
REGBANK_3A Register OUT UserAllocatable Direct 8-bit register access to GPIO48-55
REGBANK_3B Register OUT UserAllocatable Direct 8-bit register access to GPIO56-63
REGBANK_4A Register OUT UserAllocatable Direct 8-bit register access to GPIO64-71
REGBANK_4B Register OUT UserAllocatable Direct 8-bit register access to GPIO72-79
REGBANK_5A Register OUT UserAllocatable Direct 8-bit register access to GPIO80-87
REGBANK_5B Register OUT UserAllocatable Direct 8-bit register access to GPIO88-95

Total User Channels: 108 (96 GPIO + 6 VIO + 12 Register Banks)

Channel Configuration

Digital Channel Configuration

Each GPIO channel supports:

  • Direction: IN or OUT (bidirectional capability)
  • PullType: None, PullUp, or PullDown
  • PushType: PushPull or OpenDrain
  • DefaultValue: Power-on state (true/false)
  • DefaultDirection: Power-on direction

Note: Changing PullType or PushType requires a chip reset.

Voltage Output Configuration

Each VIO_BANK channel:

  • Range: 1.2V - 5.0V (values outside this range are clamped)
  • Resolution: ~1.2 mV (12-bit DAC)
  • Default: 1.8V

Register Bank Access

Register channels accept:

  • Decimal: "42" → 0x2A
  • Hexadecimal: "0x2A" → 42 decimal

Writing to a register bank updates all 8 GPIO pins in that port based on the bit pattern:

  • Bit 0 → GPIO pin 0 (or 8)
  • Bit 1 → GPIO pin 1 (or 9)
  • ...
  • Bit 7 → GPIO pin 7 (or 15)

Only OUTPUT-configured pins are updated; INPUT pins ignore register writes.

Programming Interface

Configure Individual GPIO:

ConfigureChannels(new[] {
    new DigitalChannel {
        NetName = "0.ESH10000025.GPIO00",
        Enabled = true,
        Direction = DirectionTypes.OUT,
        DefaultDirection = DirectionTypes.OUT,
        PullType = PullTypes.None,
        PushType = PushTypes.PushPull,
        Value = false
    }
});

Set Bank Voltage:

SetValues(
    new[] { "0.ESH10000025.VIO_BANK0" },
    new[] { "3.3" }  // 3.3V for Bank 0 (GPIO00-15)
);

Register Bank Write:

// Set GPIO00-07 to pattern 0b10101010 (0xAA)
SetValues(
    new[] { "0.ESH10000025.REGBANK_0A" },
    new[] { "0xAA" }  // or "170" in decimal
);

Best Practices

  1. Set VIO voltage before enabling GPIO: Ensure correct logic levels before I/O operations
  2. Use register banks for fast parallel operations: More efficient than individual GPIO writes
  3. Configure pull types during initialization: Changing pull configuration requires chip reset
  4. Group GPIO by voltage requirements: Assign similar logic levels to same bank
  5. Enable channels before use: Always set Enabled = true in ConfigureChannels

Module Initialization Sequence

On Reset(), the module performs:

  1. Clear existing channel list
  2. Setup 6 VIO_BANK DAC channels with 1.8V default
  3. Create 12 register bank channels (REGBANK_0A/B through REGBANK_5A/B)
  4. Setup 6 GPIO expander chips (U6-U11) with 96 digital channels
  5. Reset and configure all GPIO expanders
  6. Update DAC with default voltage levels
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