TPS23881 Datasheet Reference

Texas Instruments TPS23881 - Type-4 4-Pair 8-Channel PoE 2 PSE Controller with SRAM and 200 mOhm RSENSE

Datasheet: SLVSF02E - MARCH 2019 - REVISED MAY 2023

This document is used as a reference for driver validation. All register addresses, bit fields, enumerations, and conversion formulas are sourced from the TPS23881 datasheet.

Device Overview

• 8-channel PSE controller (4 ports, each port = 2 channels)
• IEEE 802.3bt Type 3/4 compliant (2-pair and 4-pair)
• I2C interface, up to 400 kHz
• RSENSE = 0.200 Ohm
• 2-Pair PCUT range: 2 W to 65 W
• 4-Pair PCUT range: 4 W to 127 W
• 4-Pair PCUT accuracy: +/-2.5%
• Capacitance measurement range: 1 uF to 12 uF
• 16 kB programmable SRAM
• ULA packaging available (TPS23881A)
• VDD: 3.0 V to 3.6 V (typ 3.3 V)
• VPWR: 44 V to 57 V
• Junction temperature: -40 C to 125 C

I2C Addressing

• Address pins: A1-A4 (internally pulled up to VDD)
• Configuration A (8-bit, nbitACC=0): Two 4-channel devices with 2 consecutive slave addresses
• Configuration B (16-bit, nbitACC=1): Single device address (A0=0)
• Broadcast address available

Operating Modes

Complete Register Map

Interrupt Registers

Event Registers

Discovery/Status Registers

Configuration Registers

Command Registers (Push-Button)

ID and Policing Registers

Detection/Fault/Remapping Registers

Priority and Power Allocation Registers

4-Pair Policing and Fault Registers

Channel Current and Voltage Registers

Configuration/Others Registers

Signature Measurement Registers

Assigned Class Registers

Auto Class Registers

Miscellaneous Registers

SRAM Registers

Detailed Register Bit Fields

0x00 - INTERRUPT Register (RO)

Active high, each bit corresponds to a particular event. Reading the corresponding event register clears the associated interrupt bit.

0x01 - INTERRUPT MASK Register (R/W)

0x02/0x03 - POWER EVENT Register (RO / CoR)

0x04/0x05 - DETECTION EVENT Register (RO / CoR)

0x06/0x07 - FAULT EVENT Register (RO / CoR)

0x08/0x09 - START/ILIM EVENT Register (RO / CoR)

0x0A/0x0B - SUPPLY/FAULT EVENT Register (RO / CoR)

Note: When RAMFLT is set, the device enters "safe mode" - all channels are turned off. SRAM must be reloaded and RAMFLT cleared before setting RAM_EN.

0x0C-0x0F - CHANNEL 1-4 DISCOVERY Registers (RO)

DETECTRESULT Enumeration

RCLASS / Requested Class Enumeration

0x10 - POWER STATUS Register (RO)

0x11 - PIN STATUS Register (RO)

0x12 - OPERATING MODE Register (R/W)

2 bits per channel:

OperatingModes Enumeration

0x13 - DISCONNECT ENABLE Register (R/W)

0x14 - DETECT/CLASS ENABLE Register (R/W)

0x15 - POWER PRIORITY / 2-PAIR PCUT DISABLE Register (R/W)

0x16 - TIMING CONFIGURATION Register (R/W)

TLIMType Enumeration

TSTARTType Enumeration

TOVLDType Enumeration

TMPDOType Enumeration

0x17 - GENERAL MASK Register (R/W)

0x18 - DETECT/CLASS RESTART Register (R/W)

0x19 - POWER ENABLE Register (R/W)

0x1A - RESET Register (R/W)

Note: For 4-pair wired ports, setting RESPn for either channel resets both channels. RESAL preserves: 0x00 (all), 0x0A/B (TSD/VPUV/VDWRN/VPUV), 0x26 (all), 0x2C/0x2E (all), 0x41 (all).

0x1B - ID Register (R/W)

0x1C - CONNECTION CHECK / AUTO CLASS STATUS Register (RO)

ConnCheckResult Enumeration

0x1E-0x21 - 2-PAIR POLICE CH1-4 Registers (R/W)

8-bit value, conversion: Power (W) = Value x 0.5

• Default: 0xFF (127.5 W)
• Range: 2 W to 65 W

0x22 - CAPACITANCE DETECTION Register (R/W)

Note: Capacitance measurement requires SRAM to be programmed. Only supported in Manual/Diagnostic mode. No measurement if resistance detection returns "valid".

0x24/0x25 - POWER-ON FAULT Register (RO / CoR)

2 bits per channel (PF4: bits 7-6, PF3: bits 5-4, PF2: bits 3-2, PF1: bits 1-0)

PowerOnFaultType Enumeration

0x26 - PORT RE-MAPPING Register (R/W)

2 bits per channel mapping logical to physical channel:

PhysicalChannel Enumeration

0x27 - MULTI-BIT PRIORITY CH 1&2 Register (R/W)

0x28 - MULTI-BIT PRIORITY CH 3&4 Register (R/W)

Same layout as 0x27 but for channels 3 and 4.

PrioType Enumeration

0x29 - 4-PAIR WIRED AND PORT POWER ALLOCATION Register (R/W)

PortPowerAllocationType Enumeration

0x2A/0x2B - 4-PAIR POLICE CH 1&2 / CH 3&4 Registers (R/W)

8-bit value, conversion: Power (W) = Value x 0.5

• Default: 0xFF (127.5 W)
• Range: 4 W to 127 W

0x2C - TEMPERATURE Register (RO)

8-bit temperature measurement.

Conversion: T (C) = -20 + N x 0.652

• Range: -20 C to ~146 C
• Update rate: ~1 Hz

0x2D - 4-PAIR FAULT CONFIGURATION Register (R/W)

0x2E - INPUT VOLTAGE Register (RO, 2 bytes)

14-bit measurement (LSByte first, MSByte second).

Conversion: VPWR (V) = N x 3.662 mV

0x30-0x3E - CHANNEL CURRENT Registers (RO, 2 bytes each)

14-bit measurement (LSByte first, MSByte second). Bits 15-14 of MSByte are reserved.

Conversion: I (A) = N x 89.445 uA (with RSENSE = 0.200 Ohm)

0x32-0x3E - CHANNEL VOLTAGE Registers (RO, 2 bytes each)

14-bit measurement (LSByte first, MSByte second). Bits 15-14 of MSByte are reserved.

Conversion: V (V) = N x 3.662 mV

0x40 - 2x FOLDBACK SELECTION Register (R/W)

0x41 - FIRMWARE REVISION Register (RO)

0x42 - I2C WATCHDOG Register (R/W)

Note: Watchdog timeout is nominally 2 seconds. Timer is reset by any SCL edge.

0x43 - DEVICE ID Register (RO)

0x44-0x47 - CHANNEL DETECT RESISTANCE Registers (RO)

8-bit detection resistance measurement per channel.

0x48-0x4B - CHANNEL DETECT CAPACITANCE Registers (RO)

8-bit capacitance measurement per channel. Requires SRAM programming.

0x4C-0x4F - CHANNEL ASSIGNED CLASS Registers (RO)

0x50 - AUTO CLASS CONTROL Register (R/W)

0x51-0x54 - CHANNEL AUTO CLASS POWER Registers (RO)

Auto class power measurement result per channel.

0x55 - ALTERNATIVE FOLDBACK Register (R/W)

0x60 - SRAM CONTROL Register (R/W)

0x62/0x63 - SRAM START ADDRESS Registers (R/W)

• 0x62: Start address LSB (SA[7:0])
• 0x63: Start address MSB (SA[15:8])

ADC Conversion Formulas

SRAM Programming Procedure

1. Set CPU_RST = 1 (reg 0x60, bit 6) to hold CPU in reset
2. Set PROG_SEL = 1 (reg 0x60, bit 7) to enable SRAM access
3. Toggle CLR_PTR (0-1-0) to reset address pointer
4. Write firmware data to reg 0x61 (continuous writes)
5. Clear PROG_SEL = 0
6. If parity is used: Set PAR_SEL = 1, toggle CLR_PTR, write parity data, clear PAR_SEL
7. Set PAR_EN = 1 if parity was loaded
8. Set RAM_EN = 1 to enable SRAM execution
9. Clear CPU_RST = 0 to release CPU
10. Verify firmware revision (reg 0x41) shows expected version
11. If reg 0x41 = 0xFF, device is in safe mode - reprogram SRAM

Auto Class Pcut Margins

• 2-Pair/Dual Signature: 2P-PCut = PAC + PAC_MARGIN
• Single Signature 4-Pair: 4P-PCut = PAC_ALTA + PAC_ALTB + PAC_MARGIN