LTC2992 Datasheet Reference

Extracted from: ltc2992.pdf (Rev A, Analog Devices)
Source: https://www.analog.com/en/products/ltc2992.html

Table 2 — ADC Resolution and LSB Step Sizes

Parameter	8-bit LSB	12-bit LSB	Full Scale (12-bit)
SENSE+ (S1, S2)	400 mV	25 mV	102.4 V
GPIO (G1–G4)	8 mV	0.5 mV	2.048 V
∆SENSE (I1, I2)	200 µV	12.5 µV	51.2 mV
Power (P1, P2)	derived	SENSE+_LSB × ∆SENSE_LSB = 25 mV × 12.5 µV = 312.5 nW	~5.24 W

Note: POWER_LSB = 25e-3 × 12.5e-6 = 3.125e-7 W (312.5 nW).
The power register holds the raw product of SENSE+_raw × ∆SENSE_raw as a 24-bit value.
Divide by RSENSE (Ω) in firmware to convert to Watts.

ADC resolution select: NADC[7] = 0 → 12-bit (default), NADC[7] = 1 → 8-bit.

Table 3 — I2C Device Addressing (7-bit)

ADR1	ADR0	7-bit Hex
H	H	0x67
H	NC	0x68
H	L	0x69
NC	H	0x6A
NC	NC	0x6B
NC	L	0x6C
L	H	0x6D
L	NC	0x6E
L	L	0x6F

H = INTVCC, NC = float, L = GND.
Mass Write address: 0x66. Alert Response address: 0x0C.

Table 4 — Register Map Summary

Register Name	Address	Bytes	R/W	Default
CTRLA	0x00	1	R/W	0x00
CTRLB	0x01	1	R/W	0x00
ALERT1	0x02	1	R/W	0x00
FAULT1	0x03	1	R/W	0x00
NADC	0x04	1	R/W	0x00
P1	0x05–0x07	3	R	—
MAX P1	0x08–0x0A	3	R	—
MIN P1	0x0B–0x0D	3	R	—
MAX P1 THRESHOLD	0x0E–0x10	3	R/W	0xFFFFFF
MIN P1 THRESHOLD	0x11–0x13	3	R/W	0x000000
I1	0x14–0x15	2	R	—
MAX I1	0x16–0x17	2	R	—
MIN I1	0x18–0x19	2	R	—
MAX I1 THRESHOLD	0x1A–0x1B	2	R/W	0xFFF0
MIN I1 THRESHOLD	0x1C–0x1D	2	R/W	0x0000
S1	0x1E–0x1F	2	R	—
MAX S1	0x20–0x21	2	R	—
MIN S1	0x22–0x23	2	R	—
MAX S1 THRESHOLD	0x24–0x25	2	R/W	0xFFF0
MIN S1 THRESHOLD	0x26–0x27	2	R/W	0x0000
G1	0x28–0x29	2	R	—
MAX G1	0x2A–0x2B	2	R	—
MIN G1	0x2C–0x2D	2	R	—
MAX G1 THRESHOLD	0x2E–0x2F	2	R/W	0xFFF0
MIN G1 THRESHOLD	0x30–0x31	2	R/W	0x0000
ADC_STATUS	0x32	1	R	—
(Reserved)	0x33	1	—	—
ALERT2	0x34	1	R/W	0x00
FAULT2	0x35	1	R/W	0x00
(Reserved)	0x36	1	—	—
P2	0x37–0x39	3	R	—
MAX P2	0x3A–0x3C	3	R	—
MIN P2	0x3D–0x3F	3	R	—
MAX P2 THRESHOLD	0x40–0x42	3	R/W	0xFFFFFF
MIN P2 THRESHOLD	0x43–0x45	3	R/W	0x000000
I2	0x46–0x47	2	R	—
MAX I2	0x48–0x49	2	R	—
MIN I2	0x4A–0x4B	2	R	—
MAX I2 THRESHOLD	0x4C–0x4D	2	R/W	0xFFF0
MIN I2 THRESHOLD	0x4E–0x4F	2	R/W	0x0000
S2	0x50–0x51	2	R	—
MAX S2	0x52–0x53	2	R	—
MIN S2	0x54–0x55	2	R	—
MAX S2 THRESHOLD	0x56–0x57	2	R/W	0xFFF0
MIN S2 THRESHOLD	0x58–0x59	2	R/W	0x0000
G2	0x5A–0x5B	2	R	—
MAX G2	0x5C–0x5D	2	R	—
MIN G2	0x5E–0x5F	2	R	—
MAX G2 THRESHOLD	0x60–0x61	2	R/W	0xFFF0
MIN G2 THRESHOLD	0x62–0x63	2	R/W	0x0000
G3	0x64–0x65	2	R	—
MAX G3	0x66–0x67	2	R	—
MIN G3	0x68–0x69	2	R	—
MAX G3 THRESHOLD	0x6A–0x6B	2	R/W	0xFFF0
MIN G3 THRESHOLD	0x6C–0x6D	2	R/W	0x0000
G4	0x6E–0x6F	2	R	—
MAX G4	0x70–0x71	2	R	—
MIN G4	0x72–0x73	2	R	—
MAX G4 THRESHOLD	0x74–0x75	2	R/W	0xFFF0
MIN G4 THRESHOLD	0x76–0x77	2	R/W	0x0000
ISUM	0x78–0x79	2	R	—
MAX ISUM	0x7A–0x7B	2	R	—
MIN ISUM	0x7C–0x7D	2	R	—
MAX ISUM THRESHOLD	0x7E–0x7F	2	R/W	0xFFF0
MIN ISUM THRESHOLD	0x80–0x81	2	R/W	0x0000
PSUM	0x82–0x84	3	R	—
MAX PSUM	0x85–0x87	3	R	—
MIN PSUM	0x88–0x8A	3	R	—
MAX PSUM THRESHOLD	0x8B–0x8D	3	R/W	0xFFFFFF
MIN PSUM THRESHOLD	0x8E–0x90	3	R/W	0x000000
ALERT3	0x91	1	R/W	0x00
FAULT3	0x92	1	R/W	0x00
ALERT4	0x93	1	R/W	0x00
FAULT4	0x94	1	R/W	0x00
GPIO_STATUS	0x95	1	R	—
GPIO_CONTROL	0x96	1	R/W	0x03
GPIO4_CTRL	0x97	1	R/W	0x00
MFR_SPECIAL_ID (MSB)	0xE7	1	R	0x62
MFR_SPECIAL_ID (LSB)	0xE8	1	R	—

Note: For all 2- and 3-byte registers, MSB is at the lowest address (big-endian).

Table 5 — CTRLA Register (0x00)

Bits	Name	Operation
CTRLA[7]	Offset Calibration	1 = Calibrate on Demand; 0 = Every Conversion (default)
CTRLA[6:5]	Measurement Mode	11 = Shutdown; 10 = Single Cycle; 01 = Snapshot; 00 = Continuous Scan (default)
CTRLA[4:3]	VADC Channels (Continuous)	see table below
CTRLA[2:0]	VADC Channels (Snapshot)	see table below

CTRLA[4:3] — Continuous Scan VADC channel selection

[4:3]	VADC channels	P1 uses	P2 uses
00	SENSE1+, SENSE2+, G1–G4 (default)	SENSE1+ × ∆SENSE1	SENSE2+ × ∆SENSE2
01	SENSE1+, SENSE2+, G1, G2	SENSE1+ × ∆SENSE1	SENSE2+ × ∆SENSE2
10	G1, G2 only	G1 × ∆SENSE1	G2 × ∆SENSE2
11	G1, G2, G3, G4 only	G1 × ∆SENSE1	G2 × ∆SENSE2

GPIO ADC usage: GPIO1–4 are always analog-scanned by VADC when included in the channel selection above.
There is no separate per-pin ADC enable in GPIO_CONTROL (0x96).

Table 6 — CTRLB Register (0x01)

Bit	Name	Operation
CTRLB[7]	ALERT Clear Enable	1 = Clear ALERT pin when device is addressed by master; 0 = Disable (default)
CTRLB[6]	Reserved	Always returns 0
CTRLB[5]	Cleared on Read Control	1 = FAULT registers cleared on read; 0 = not affected (default)
CTRLB[4]	Stuck Bus Timeout	1 = Allow exit from shutdown when stuck-bus timer fires; 0 = Disable (default)
CTRLB[3]	Peak Hold Values Reset	1 = Reset ALL Min/Max registers (self-cleared); 0 = Disable (default)
CTRLB[2:1]	Reserved	Always returns 00
CTRLB[0]	Reset	1 = Reset ALL internal registers (self-cleared); 0 = Disable (default)

Table 9 — NADC Register (0x04)

Bit	Name	Operation
NADC[7]	ADC Resolution	1 = 8-bit; 0 = 12-bit (default)
NADC[6:0]	Reserved	Always returns 0

Table 10 — ADC_STATUS Register (0x32) — Read Only, Clear-on-Read

Bit	Name
AS[7]	IADCs Data Ready
AS[6]	VADC Data Ready
AS[5]	GPIO4 Data Ready
AS[4]	GPIO3 Data Ready
AS[3]	GPIO2 Data Ready
AS[2]	GPIO1 Data Ready
AS[1]	SENSE2+ Data Ready
AS[0]	SENSE1+ Data Ready

Table 17 — GPIO_STATUS Register (0x95) — Read Only

Bit	Name
GS[7:4]	Reserved (0)
GS[3]	GPIO1 State
GS[2]	GPIO2 State
GS[1]	GPIO3 State
GS[0]	GPIO4 State

Table 18 — GPIO IO CONTROL Register (0x96) — Default: 0x03

Bit	Name	Operation
GIO[7]	GPIO1 Output	1 = Pulls Low; 0 = Hi-Z (default)
GIO[6]	GPIO2 Output	1 = Pulls Low; 0 = Hi-Z (default)
GIO[5:4]	GPIO3 Configuration	11 = Pull low on data ready (cleared by reading ADC_STATUS 0x32); 10 = 128 µs low pulse on data ready; 01 = 16 µs low pulse on data ready; 00 = General Purpose I/O (default)
GIO[3]	GPIO1 Alert Polarity	1 = Alert on GPIO1 high; 0 = Alert on GPIO1 low (default)
GIO[2]	GPIO2 Alert Polarity	1 = Alert on GPIO2 high; 0 = Alert on GPIO2 low (default)
GIO[1]	GPIO3 Alert Polarity	1 = Alert on GPIO3 high (default); 0 = Alert on GPIO3 low
GIO[0]	GPIO3 Output	1 = Pulls Low (default); 0 = Hi-Z

Default 0x03 = GIO[1]=1 (GPIO3 alert polarity high) + GIO[0]=1 (GPIO3 output pull-low).
GPIO4 output is not in this register — it is in GPIO4_CTRL (0x97).

Table 19 — GPIO4 CONTROL Register (0x97) — Default: 0x00

Bit	Name	Operation
GC[7]	Alert Generated	1 = Alert generated (latched); clear by writing 0 or setting CTRLB[7]
GC[6]	GPIO4 Output	1 = Pulls Low; 0 = Hi-Z (default)
GC[5:0]	Reserved	Always returns 000000

Table 20 — 2-Byte Register Data Format (12-bit mode)

MSB byte:  [Data(11) Data(10) Data(9) Data(8) Data(7) Data(6) Data(5) Data(4)]
LSB byte:  [Data(3)  Data(2)  Data(1) Data(0) 0       0       0       0      ]

Extract: raw12 = (MSBbyte << 4) | (LSBbyte >> 4) — i.e., assemble big-endian 16-bit then shift right 4.

Table 21 — 3-Byte Register Data Format (12-bit mode, Power registers)

MSB2 byte: [Data(23)..Data(16)]
MSB1 byte: [Data(15)..Data(8) ]
LSB  byte: [Data(7) ..Data(0) ]

Extract: raw24 = (MSB2 << 16) | (MSB1 << 8) | LSB — full 24-bit, no shift.

Key Design Notes for Driver Implementation

Wire format is big-endian (MSB at lowest address). Read MSB first; write MSB first.
12-bit 2-byte registers (I, S, G): assemble big-endian 16-bit then >> 4 to get 12-bit count.
24-bit 3-byte registers (P, PSUM): assemble big-endian 24-bit, no shift.
GPIO output control (0x96 GIO[7], GIO[6], GIO[0]) and GPIO4 output (0x97 GC[6]) must be set to Hi-Z (0) when the corresponding GPIO pin is used as an ADC input, or the output latch will pull the pin low and corrupt the ADC reading.
Software reset (CTRLB[0]=1) resets all config registers including GPIO_CONTROL to their defaults. Always configure GPIO output states after reset.
GPIO_CONTROL default = 0x03: GPIO3 output = pull-low, GPIO3 alert polarity = high. GPIO1/2 outputs = Hi-Z.